Dual silicide liner flow for enabling low contact resistance

ABSTRACT

A method for fabricating a semiconductor device includes depositing a sacrificial liner in self-aligned contact openings in first and second regions. The openings are filled with a sacrificial material. The second region is blocked with a first mask to remove the sacrificial material from the first region. The first mask is removed from the second region, and the sacrificial liner is removed from the first region. A first liner is formed in the openings of the first region, and first contacts are formed in the first region on the first liner. The first region is blocked with a second mask to remove the sacrificial material from the second region. The second mask is removed from the first region, and the sacrificial liner is removed from the second region. A second liner is formed in the openings of the second region, and second contacts are formed in the second region.

BACKGROUND

Technical Field

The present invention relates to semiconductor processing, and moreparticularly to methods and devices for a dual liner with improvedcontact resistance and reduced pinch off.

Description of the Related Art

In complementary metal oxide semiconductor processing (CMOS), n-type andp-type devices are formed together. These devices may share processingsteps at certain points in a workflow but need to be processedseparately in others. One process where the n-type and p-type devicesare processed separately includes dual liner integration for formingliners for self-aligned contact (SAC) formation.

A first liner for n-type field effect transistors (NFETs) is appliedover both NFETs and p-type field effect transistors (PFETs). The firstliner is then removed from the PFETs followed by a second liner over thePFETs and the NFETs. With shrinking contact size, the NFET gets pinchedoff due to the presence of both liners. Pinched off means that thecontact hole gets blocked preventing the contact hole from being filledwith contact material. This also increases contact resistance and couldresult in device failure.

SUMMARY

A method for fabricating a semiconductor device includes depositing asacrificial liner in self-aligned contact openings in first and secondregions, where the first region includes a first device type and thesecond region includes a second device type. The openings are filledwith a sacrificial material. The second region is blocked with a firstmask to remove the sacrificial material from the first region. The firstmask is removed from the second region, and the sacrificial liner isremoved from the first region. A first liner is formed in the openingsof the first region, and first contacts are formed in the first regionon the first liner. The first region is blocked with a second mask toremove the sacrificial material from the second region. The second maskis removed from the first region, and the sacrificial liner is removedfrom the second region. A second liner is formed in the openings of thesecond region, and second contacts are formed in the second region.

Another method for fabricating a semiconductor device includespatterning an interlevel dielectric layer to form self-aligned contactopenings over field effect transistors; depositing a sacrificial linerin the self-aligned contact openings; filling the self-aligned contactopenings with a sacrificial material; blocking a p-type field effecttransistor (PFET) region with a first mask to remove the sacrificialmaterial from an n-type field effect transistor (NFET) region; removingthe first mask from the PFET region and the sacrificial liner from theNFET region; forming a first liner in the self-aligned contact openingsof the NFET region, which contacts underlying regions; forming firstcontacts in the NFET region on the first liner; blocking the NFET regionwith a second mask to remove the sacrificial material from the PFETregion; removing the second mask from the NFET region and thesacrificial liner from the PFET region; forming a second liner in theopenings of the PFET region, which contacts underlying regions; andforming second contacts in the PFET region.

A semiconductor device includes a first region including n-type fieldeffect transistors (NFETs), and a second region including p-type fieldeffect transistors (PFETs). A first liner is formed in the self-alignedcontact openings of the NFETs, and first contacts are formed in theself-aligned contact openings of the NFETs on the first liner. A secondliner is formed in the self-aligned contact openings of the PFETs, andsecond contacts are formed in the self-aligned contact openings of thePFETs on the second liner. The self-aligned contact openings includeonly one liner in the first region and only one liner in the secondregion, and the first liner and the second liner include differentmaterials.

These and other features and advantages will become apparent from thefollowing detailed description of illustrative embodiments thereof,which is to be read in connection with the accompanying drawings.

BRIEF DESCRIPTION OF THE SEVERAL VIEWS OF THE DRAWINGS

The disclosure will provide details in the following description ofpreferred embodiments with reference to the following figures wherein:

FIG. 1 is a cross-sectional view of a semiconductor device having n-typefield effect transistors (NFETs) and p-type field effect transistors(PFETs) formed thereon in accordance with the present principles;

FIG. 2 is a cross-sectional view of the semiconductor device of FIG. 1having self-aligned contact openings formed for NFETs and PFETs inaccordance with the present principles;

FIG. 3 is a cross-sectional view of the semiconductor device of FIG. 2having the self-aligned contact openings lined with a sacrificial linerin accordance with the present principles;

FIG. 4 is a cross-sectional view of the semiconductor device of FIG. 3having the self-aligned contact openings filled with a sacrificialmaterial in accordance with the present principles;

FIG. 5 is a cross-sectional view of the semiconductor device of FIG. 4having a PFET region blocked with a block mask in accordance with thepresent principles;

FIG. 6 is a cross-sectional view of the semiconductor device of FIG. 5having the sacrificial material removed from the NFET region inaccordance with the present principles;

FIG. 7 is a cross-sectional view of the semiconductor device of FIG. 6having a liner and a main conductor formed in the self-aligned contactholes in the NFET region in accordance with the present principles;

FIG. 8 is a cross-sectional view of the semiconductor device of FIG. 7having a top surface planarized to form contacts in the NFET region inaccordance with the present principles;

FIG. 9 is a cross-sectional view of the semiconductor device of FIG. 8having a PFET region blocked with a block mask and the sacrificialmaterial removed from the PFET region in accordance with the presentprinciples;

FIG. 10 is a cross-sectional view of the semiconductor device of FIG. 9having a liner and a main conductor formed in the self-aligned contactholes in the PFET region in accordance with the present principles;

FIG. 11 is a cross-sectional view of the semiconductor device of FIG. 10having a top surface planarized to form contacts in the PFET region inaccordance with the present principles; and

FIG. 12 is a block/flow diagram showing methods for forming asemiconductor device in accordance with illustrative embodiments.

DETAILED DESCRIPTION

In accordance with the present principles, devices and methods forforming these devices are described that provide flexibility inintegrating n-type and p-type devices. In one useful embodiment,formation of dual epitaxial growth or dual epi is enabled by the processflow. In one embodiment, a sacrificial material or mask (e.g., TiN) isformed and used in combination with a sacrificial liner, e.g., an oxide.The sacrificial material and liner are deposited in contact openings orholes so as to not allow metals to touch epitaxially grown materials inregions located within the holes. The regions may include silicidedjunctions, source and drain regions, trench silicide contacts, etc.

The sacrificial material is employed to remove the liner selectivelywhile covering a device not being processed (one of n-type field effecttransistors (NFETs) or p-type field effect transistors (PFETs)). Thesacrificial liner may be removed during actual metal pre-cleanprocessing. This sacrificial liner ensures no interface mixing prior toactual silicide liner deposition. A first FET is covered with thesacrificial material during this process. Contacts are formed bydepositing conductive material and planarizing the conductive material.The process is repeated to form a liner and contacts in a second FETstructure. In some embodiments, contacts are formed by depositingconductive material and planarizing the conductive material in separateprocesses for the NFETs and the PFETs. This provides the possibility ofusing different contact materials for NFETs and PFETs.

It is to be understood that the present invention will be described interms of a given illustrative architecture; however, otherarchitectures, structures, substrate materials and process features andsteps may be varied within the scope of the present invention.

It will also be understood that when an element such as a layer, regionor substrate is referred to as being “on” or “over” another element, itcan be directly on the other element or intervening elements may also bepresent. In contrast, when an element is referred to as being “directlyon” or “directly over” another element, there are no interveningelements present. It will also be understood that when an element isreferred to as being “connected” or “coupled” to another element, it canbe directly connected or coupled to the other element or interveningelements may be present. In contrast, when an element is referred to asbeing “directly connected” or “directly coupled” to another element,there are no intervening elements present.

The present embodiments may include a design for an integrated circuitchip, which may be created in a graphical computer programming language,and stored in a computer storage medium (such as a disk, tape, physicalhard drive, or virtual hard drive such as in a storage access network).If the designer does not fabricate chips or the photolithographic masksused to fabricate chips, the designer may transmit the resulting designby physical means (e.g., by providing a copy of the storage mediumstoring the design) or electronically (e.g., through the Internet) tosuch entities, directly or indirectly. The stored design is thenconverted into the appropriate format (e.g., GDSII) for the fabricationof photolithographic masks, which typically include multiple copies ofthe chip design in question that are to be formed on a wafer. Thephotolithographic masks are utilized to define areas of the wafer(and/or the layers thereon) to be etched or otherwise processed.

Methods as described herein may be used in the fabrication of integratedcircuit chips. The resulting integrated circuit chips can be distributedby the fabricator in raw wafer form (that is, as a single wafer that hasmultiple unpackaged chips), as a bare die, or in a packaged form. In thelatter case the chip is mounted in a single chip package (such as aplastic carrier, with leads that are affixed to a motherboard or otherhigher level carrier) or in a multichip package (such as a ceramiccarrier that has either or both surface interconnections or buriedinterconnections). In any case the chip is then integrated with otherchips, discrete circuit elements, and/or other signal processing devicesas part of either (a) an intermediate product, such as a motherboard, or(b) an end product. The end product can be any product that includesintegrated circuit chips, ranging from toys and other low-endapplications to advanced computer products having a display, a keyboardor other input device, and a central processor.

It should also be understood that material compounds will be describedin terms of listed elements, e.g., NiPtSi, NiSi, PtSi, etc. Thesecompounds include different proportions of the elements within thecompound. In addition, other elements may be included in the compoundand still function in accordance with the present principles. Thecompounds with additional elements will be referred to herein as alloys.

Reference in the specification to “one embodiment” or “an embodiment” ofthe present principles, as well as other variations thereof, means thata particular feature, structure, characteristic, and so forth describedin connection with the embodiment is included in at least one embodimentof the present principles. Thus, the appearances of the phrase “in oneembodiment” or “in an embodiment”, as well any other variations,appearing in various places throughout the specification are notnecessarily all referring to the same embodiment.

It is to be appreciated that the use of any of the following “/”,“and/or”, and “at least one of”, for example, in the cases of “A/B”, “Aand/or B” and “at least one of A and B”, is intended to encompass theselection of the first listed option (A) only, or the selection of thesecond listed option (B) only, or the selection of both options (A andB). As a further example, in the cases of “A, B, and/or C” and “at leastone of A, B, and C”, such phrasing is intended to encompass theselection of the first listed option (A) only, or the selection of thesecond listed option (B) only, or the selection of the third listedoption (C) only, or the selection of the first and the second listedoptions (A and B) only, or the selection of the first and third listedoptions (A and C) only, or the selection of the second and third listedoptions (B and C) only, or the selection of all three options (A and Band C). This may be extended, as readily apparent by one of ordinaryskill in this and related arts, for as many items listed.

Referring now to the drawings in which like numerals represent the sameor similar elements and initially to FIG. 1, a cross-sectional view of asemiconductor device 10 is shown in accordance with the presentprinciples. The device 10 includes a substrate 16, which may include abulk substrate 15 having a dielectric layer 17 formed thereon, or thesubstrate 15, the dielectric layer 17 and a semiconductor layer to formfins 18 may be part of a semiconductor-on-insulator (SOI) substrate 16.The substrate 15 may include any suitable material, and in particular,may include Si, Ge, SiGe, SiC, III-V material, etc. The fins 18 mayinclude any suitable semiconductor material, and in particular mayinclude Si, Ge, SiGe, etc. The dielectric layer 17 may include an oxide,although other dielectric materials may be employed.

The fins 18 form channel regions for field effect transistors (FETs)formed thereon. The device 10 may include n-type FETs (NFETs) formed inan NFET region 12 and p-type FETs (PFETs) formed in a PFET region 14.Gate structures 32 are formed over the fins 18 and may include gateconductors 20, 22. A gate dielectric 25 which may cover sidewalls of thegate conductor 22 and is placed between the gate conductors 20, 22 andthe fin 18. The gate conductor 20 may include a work function metal,such as e.g., Pt, Ag, etc. and the gate conductor 22 may include a mainconductor, e.g., W, etc. The gate structures 32 include spacers 24 and acap 26, which may include silicon nitride material.

Between gates 32 in the NFET region 12, silicided junctions, source anddrain regions, or trench silicide contacts 29 (hereinafter referred toas regions 29) are formed (depending on the design). Between gates 32 inthe PFET region 14, silicided junctions, source and drain regions, ortrench silicide contacts 30 (hereinafter referred to as regions 30) areformed (depending on the design). The regions 29 and 30 may be formed byepitaxial growth and may be doped in-situ. The regions 29 and 30 mayinclude different materials, e.g., the NFET may include TiSi, while thePFET may include PtSi, NiSi, or NiPtSi. Regions 29, 30 may have beenprocessed already or may be processed in later steps.

A dielectric layer 34, e.g., an interlevel dielectric (ILD), is formedover the NFET region 12 and the PFET region 14. The dielectric layer 34may include an oxide, although other dielectric materials may beemployed.

Referring to FIG. 2, the dielectric layer 34 is patterned to formopenings 36 down to the regions 29 and 30. The openings 36 are formed bya reactive ion etch process in accordance with a lithographically formedmask (not shown).

Referring to FIG. 3, a sacrificial liner 38 is formed in the openings 36in both the NFET region 12 and the PFET region 14. The sacrificial liner38 lines the openings and exposes portions of the regions 29, 30. Thesacrificial liner 38 protects the surface (silicide) of the regions 29,30 from being contaminated with any material. The sacrificial liner 38may include an oxide material.

Referring to FIG. 4, a sacrificial material 40 is deposited in theopenings 36 on the sacrificial liner 38 and on a top surface of thedevice 10 in both the NFET region 12 and the PFET region 14. Thesacrificial material 40 is selected to be easily removed by standardcleaning or etching processes, such as standard clean 1 (SC1). In oneembodiment, the sacrificial material 40 includes TiN although ofmaterials may be employed.

Referring to FIG. 5, a blocking mask 42 is deposited over thesacrificial material 40 in both the NFET region 12 and the PFET region14. The blocking mask 42 is then patterned (e.g., using lithographicprocessing) to remove the blocking mask 42 from the NFET region 12. Theblocking mask 42 may include a dielectric material, a resist material orany other suitable material configured to withstand processing in theNFET region 12.

Referring to FIG. 6, the exposed NFET region 12 is subjected to an etchprocess, such as a SC1 process or a different etch process to remove thesacrificial material 40. Once the sacrificial material 40 is removednormal NFET processing may take place while the PFET region 14 isblocked. The NFET region 12 may be processed at this point by performingNFET epitaxial deposition and/or silicide formation. Growth/depositionof trench epitaxial material or deposition of NFET silicide metal orboth may occur or other processing may be performed depending on thedesign.

Referring to FIG. 7, the blocking mask 42 is selectively removed fromthe PFET region 14. A metal preclean process is performed, which removessacrificial liner 38 from the NFET region 12. The preclean process mayinclude, e.g., a gas cluster ion beam (GCIB) process or SiCoNi™ etchprocess. After removing the sacrificial liner 38 from the NFET region12, a liner silicide 44 is formed in the openings 36 (FIG. 3) and overthe sacrificial material 40 in the PFET region 14. The liner silicide 44may include Ti, TiN, or other materials suitable for formation of a lowcontact resistance connection with regions 29. The silicide liner 44 isfollowed by a main conductor deposition, which deposits a conductivematerial 46 over the silicide liner 44. The conductive material 46 mayinclude W, although other conductive materials may be employed.

Referring to FIG. 8, a planarization process is performed to reduce atop surface down to the ILD 34. The planarization process may include arecess etch or a chemical mechanical polish (CMP). The planarizationprocess forms contacts 50 (e.g., self-aligned contacts (SAC)) for theNFETs in the NFET region 12.

Referring to FIG. 9, a blocking mask 52 is deposited over the device 10in both the NFET region 12 and the PFET region 14. The blocking mask 52is then patterned (e.g., using lithographic processing) to remove theblocking mask 52 from the PFET region 14. The blocking mask 52 mayinclude a dielectric material, a resist material or any other suitablematerial configured to withstand processing in the PFET region 14.

The exposed PFET region 14 is subjected to an etch process, such as aSC1 process or a different etch process to remove the sacrificialmaterial 40 from openings 36. Once the sacrificial material 40 isremoved normal PFET processing may take place while the NFET region 12is blocked. The PFET region 14 may be processed at this point byperforming PFET epitaxial deposition and/or silicide formation.Growth/deposition of trench epitaxial material or deposition of PFETsilicide metal or both may occur or other processing may be performeddepending on the design.

Referring to FIG. 10, the blocking mask 52 is selectively removed fromthe NFET region 12. A metal preclean process is performed, which removessacrificial liner 38 from the PFET region 14. The preclean process mayinclude, e.g., a gas cluster ion beam (GCIB) process or SiCoNi™ etchprocess. After removing the sacrificial liner 38 from the PFET region14, a liner material 54 is formed in the openings 36 (FIG. 3) and overthe contacts 50 in the NFET region 12. The liner material 44 may includeNi, NiPt, Pt, or other materials suitable for formation of a low contactresistance connection with regions 30. The liner material 54 is followedby a main conductor deposition, which deposits a conductive material 56over the liner material 54. The conductive material 56 may include W,although other conductive materials may be employed. In one embodiment,the materials 46 and 56 may be the same material (e.g., W). In otherembodiments, the materials 46 and 56 may include different materials(e.g., Ti, W, TiC, Al, Ag, Pt, etc.).

Referring to FIG. 11, a planarization process is performed to reduce atop surface down to the ILD 34. The planarization process may include arecess etch or a chemical mechanical polish (CMP). The planarizationprocess forms contacts 60 (e.g., self-aligned contacts (SAC)) for thePFETs in the PFET region 14.

The structure provided in FIG. 11 includes dual liner materials 44, 54formed separately for NFETs and PFETs. Since the liners 44 and 54 areformed separately, they can be thinner and prevent pinch off for theformation of the main conductor (e.g., conductors 46, 56). Withshrinking contact size, thin liners on each type of contact 50, 60ensures more room for the main conductor (lower resistance). Inaddition, only one liner is employed in any trench, hence preventingbuildup of materials that could result in pinch off, lower contactresistance and possibly device failure.

Referring to FIG. 12, methods for fabricating a semiconductor device areshown in accordance with the present principles. In some alternativeimplementations, the functions noted in the blocks may occur out of theorder noted in the figures. For example, two blocks shown in successionmay, in fact, be executed substantially concurrently, or the blocks maysometimes be executed in the reverse order, depending upon thefunctionality involved. It will also be noted that each block of theblock diagrams and/or flowchart illustration, and combinations of blocksin the block diagrams and/or flowchart illustration, can be implementedby special purpose hardware-based systems that perform the specifiedfunctions or acts or carry out combinations of special purpose hardwareand computer instructions.

In block 102, self-aligned contact openings are formed by patterning aninterlevel dielectric layer. In block 104, a sacrificial liner isdeposited in self-aligned contact openings in first and second regions,where the first region includes a first device type (e.g., NFET) and thesecond region includes a second device type (e.g., PFET). It should beunderstood that while the present disclosure describes processing theNFET region first; however, the processing order may be reversed so thatthe PFET region is processed first. Underlying regions in theself-aligned contact openings remain uncontaminated by employing thesacrificial liner for protection. The sacrificial liner may include anoxide.

In block 106, the self-aligned contact openings are filled with asacrificial material, e.g., TiN. In block 108, the second region isblocked with a first mask to remove the sacrificial material from thefirst region. In block 110, the first mask is removed from the secondregion, and the sacrificial liner is removed from the first region.

In block 112, a first liner is formed in the openings of the firstregion. If the first liner is employed for NFETs, the first liner mayinclude Ti or TiN. In block 114, first contacts are formed in the firstregion on the first liner. In block 116, the first region is blockedwith a second mask to remove the sacrificial material from the secondregion. In block 118, the second mask is removed from the first region,and the sacrificial liner is removed from the second region. In block120, a second liner is formed in the openings of the second region. Ifthe second liner is employed for PFETs, the second liner may include Pt,Ni or a combination thereof. In block 122, second contacts are formed inthe second region. The first contacts and the second contacts mayinclude the same or different materials. The self-aligned contactopenings include only one liner in the first region and only one linerin the second region, and the first liner and the second liner includedifferent materials. In one embodiment, the first liner and the secondliner form silicides with underlying regions. In block 124, processingcontinues to complete the device.

Having described preferred embodiments for a dual silicide liner flowfor enabling low contact resistance (which are intended to beillustrative and not limiting), it is noted that modifications andvariations can be made by persons skilled in the art in light of theabove teachings. It is therefore to be understood that changes may bemade in the particular embodiments disclosed which are within the scopeof the invention as outlined by the appended claims. Having thusdescribed aspects of the invention, with the details and particularityrequired by the patent laws, what is claimed and desired protected byLetters Patent is set forth in the appended claims.

1. A semiconductor device, comprising: a first region including n-typefield effect transistors (NFETs); a second region including p-type fieldeffect transistors (PFETs); a first liner formed in the self-alignedcontact openings of the NFETs; first contacts formed in the self-alignedcontact openings of the NFETs on the first liner; a second liner formedin the self-aligned contact openings of the PFETs; and second contactsformed in the self-aligned contact openings of the PFETs on the secondliner, wherein the self-aligned contact openings include only one linerin the first region and only one liner in the second region and thefirst liner and the second liner include different materials.
 2. Thedevice as recited in claim 1, wherein the first liner includes Ti. 3.The device as recited in claim 1, wherein the first liner includes TiN4. The device as recited in claim 1, wherein the second liner includesPt.
 5. The device as recited in claim 1, wherein the second linerincludes Ni.
 6. The device as recited in claim 1, wherein the secondliner includes a combination of Ni and Pt.
 7. The device as recited inclaim 1, wherein the first contacts and the second contacts includedifferent materials.
 8. The device as recited in claim 1, wherein thefirst liner and the second liner form silicides with underlying regions.9. The device as recited in claim 1, wherein the first contacts areself-aligned contacts.
 10. The device as recited in claim 1, wherein thesecond contacts are self-aligned contacts.